CISC and RISC Architecture

The sequences of micro instructions can be directly executed at the hardware level, and therefore considered to be the lowest level of the operations. How ever the instructions of the programs are given as macro instructions, thus required to be translated into micro instruction sequence before execution. The translation can be done through an interpreter program. This enables the co-existence of hardware and software, and also gives provisions to implement different architectures with various organizations. The variety necessitates different levels of hardware-software interactions.

CISC and RISC

In late 1970s, Complex Instruction Sets were used in most of machine designs. In order to convert these macro instruction sets to basic register-register or register-memory operations micro instruction interpreters are used. These micro-instructions are directly executable at hardware level. The computers which used complex instruction sets were called ‘Complex Instruction Set Computers (CISC). The major issue was that these macro-instructions were not executed most of the time in real programs. The interpretation stage reduces the efficiency of the execution, thus affected the

performance of the computer.

The suggested resolution was to produce small instruction sets which could be executed efficiently on hardware. One objective was to eliminate the interpretation stage of macro-instructions. This was called Reduced Instruction Set Computers (RISC). The count of instructions can be greater than the CISC, but, as the instructions are ready to execute, and do not need further interpretations the efficiency is considerably greater, regardless of the no. of instructions. Thus RISC ensures faster execution.

However, CISC were not completely brushed off, instead, both CISC and RISC architectures are used as appropriate, where RISC is applied for simplest instructions and CISC for more complex ones.